Signal flow driven circuit analysis and partition technique

ABSTRACT

A signal flow driven circuit analysis and partition technique are provided for mixed signal circuit performance optimization, yield enhancement and layout optimization. The inventive device includes automatic partition of mixed signal integrated circuits based on functional blocks, automatic identification of critical signal path in analog/RF circuits, automatic identification of fundamental unit circuits, automatic identification of matching and symmetry requirement. Circuit partition automatically partitions a mixed signal circuit into blocks based on their functionality. Identification of signal flow is achieved by automatically tracing the signal flow and identifies the critical path based a set of rules. Various building blocks of known characteristics and optimization requirement can also be automatically obtained. By tracing the signal path, matching and symmetry requirement and parasitic loading requirement at critical circuit nodes can also be automatically generated.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of the filingdate of provisional patent application Serial No. 60/442,306 filed Jan.27, 2003.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates generally to circuit analysis andpartition and more specifically, it relates to a signal flow drivencircuit analysis and partition technique for mixed-signal circuitperformance optimization, yield enhancement and layout optimization.

[0004] 2. Description of the Related Art

[0005] It can be appreciated that circuit analysis and partition havebeen in use for years. Typically, circuit analysis and partition arecomprised of manual partition of circuit blocks based on theirfunctionality and physical requirement during the circuit design andlayout stages. For RF/Analog circuit blocks, identifying the criticalsignal flow is either not performed or implicitly identified at thelayout stages manually by layout designers. Circuit optimization iscommonly performed by trial-and-error with heavy-duty emulators likeSPICE or Spectre.

[0006] The main problem with conventional circuit analysis and partitionare that the mixed signal circuit designs often suffer sub-optimal blocklevel partition or no partition at all due to lack of an automatedsolution. This results in either compromised performance of the productor excessive physical area of the layout. Another problem withconventional circuit analysis and partition are that massive numericalsimulations are needed in optimizing the performance of the circuit.Simulation can be prohibitively time and/or computation power intensive,that performance optimization may not be feasible for certain scale ofcircuits. Another problem with conventional circuit analysis andpartition are that it is difficult to assure high quality layout, as itis up to the layout designer to manually identify the critical signalpath during layout stage, which is largely dependent on designers'experience level and extremely error prone.

[0007] While these devices may be suitable for the particular purpose towhich they address, they are not as suitable for mixed signal circuitperformance optimization, yield enhancement and layout optimization. Themain problem with conventional circuit analysis and partition are thatthe mixed signal circuit designs often suffer sub-optimal block levelpartition or no partition at all due to lack of an automated solution.This results in either compromised performance of the product orexcessive physical area of the layout. Another problem is that massivenumerical simulations are needed in optimizing the performance of thecircuit. Simulation can be prohibitively time and/or computation powerintensive, that performance optimization may not be feasible for certainscale of circuits. Also, another problem is that it is difficult toassure high quality layout, as it is up to the layout designer tomanually identify the critical signal path during layout stage, which islargely dependent on designers' experience level and extremely errorprone.

[0008] In these respects, the signal flow driven circuit analysis andpartition technique according to the present invention substantiallydeparts from the conventional concepts and designs of the prior art, andin so doing provides an apparatus primarily developed for the purpose ofmixed signal circuit performance optimization, yield enhancement andlayout optimization.

SUMMARY OF THE INVENTION

[0009] In view of the foregoing disadvantages inherent in the knowntypes of circuit analysis and partition now present in the prior art,the present invention provides a new signal flow driven circuit analysisand partition technique construction wherein the same can be utilizedfor mixed signal circuit performance optimization, yield enhancement andlayout optimization.

[0010] The general purpose of the present invention, which will bedescribed subsequently in greater detail, is to provide a new signalflow driven circuit analysis and partition technique that has many ofthe advantages of the circuit analysis and partition mentionedheretofore and many novel features that result in a new signal flowdriven circuit analysis and partition technique which is notanticipated, rendered obvious, suggested, or even implied by any of theprior art circuit analysis and partition, either alone or in anycombination thereof.

[0011] To attain this, the present invention generally comprisesautomatic partition of mixed signal integrated circuits based onfunctional blocks, automatic identification of critical signal path inanalog/RF circuits, automatic identification of fundamental unitcircuits, automatic identification of matching and symmetry requirement.Circuit partition automatically partitions a mixed signal circuit intoblocks based on their functionality. Identification of signal flow isachieved by automatically tracing the signal flow and identification ofthe critical path is based on a set of rules. Various building blocks ofknown characteristics and optimization requirement can also beautomatically obtained. By tracing the signal path, matching andsymmetry requirement and parasitic loading requirement at criticalcircuit nodes can also be automatically generated.

[0012] There has thus been outlined, rather broadly, the more importantfeatures of the invention in order that the detailed description thereofmay be better understood, and in order that the present contribution tothe art may be better appreciated. There are additional features of theinvention that will be described hereinafter.

[0013] In this respect, before explaining at least one embodiment of theinvention in detail, it is to be understood that the invention is notlimited in its application to the details of construction and to thearrangements of the components set forth in the following description orillustrated in the drawings. The invention is capable of otherembodiments and of being practiced and carried out in various ways.Also, it is to be understood that the phraseology and terminologyemployed herein are for the purpose of the description and should not beregarded as limiting.

[0014] A primary object of the present invention is to provide a signalflow driven circuit analysis and partition technique that will overcomethe shortcomings of the prior art devices.

[0015] An object of the present invention is to provide a signal flowdriven circuit analysis method by tracing signal flow.

[0016] An object of the present invention is to provide automaticcircuit partition technique based on functionality and criticality.

[0017] An object of the present invention is to provide automaticcircuit analysis to identify critical nodes, critical nets, criticalcomponents for performance assessment, yield enhancement, layoutconstrains generation, and circuit physical layout floor planning.

[0018] An object of the present invention is to provide a signal flowdriven circuit analysis and partition technique for mixed signal circuitperformance optimization, yield enhancement and layout optimization.

[0019] Another object is to provide a signal flow driven circuitanalysis and partition technique that automatically identifies thecritical signal path in the RF/Analog integrated circuits.

[0020] Another object is to provide a signal flow driven circuitanalysis and partition technique that automatically identifiesfundamental circuit units such as current mirrors, differential pairs,voltage or current references and stages of amplifiers etc.

[0021] Another object is to provide a signal flow driven circuitanalysis and partition technique that automatically partitions a mixedsignal circuit into digital (logic) section and analog/RF section.

[0022] Another object is to provide a signal flow driven circuitanalysis and partition technique that automatically identifies matchingdevices and symmetry requirement for layout purposes.

[0023] Another object is to provide a signal flow driven circuitanalysis and partition technique that automatically partition theanalog/RF circuit section to critical signal path section and biasingcircuit section for layout and/or circuit optimization purposes.

[0024] Other objects and advantages of the present invention will becomeobvious to the reader and it is intended that these objects andadvantages within the scope of the present invention.

[0025] To the accomplishment of the above and related objects, thisinvention may be embodied in the form illustrated in the accompanyingdrawings, attention being called to the fact, however, that the drawingsare illustrative only, and that changes may be made in the specificconstruction illustrated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Various other objects, features and attendant advantages of thepresent invention will become fully appreciated as the same becomesbetter understood when considered in conjunction with the accompanyingdrawings, in which like reference characters designate the same orsimilar parts throughout the several views, and wherein:

[0027]FIG. 1 Signal Flow Driven Circuit Analysis and Partition FlowChart

[0028]FIG. 2 Means of Circuit Performance Assessment and Circuit YieldEnhancement Flow Chart

[0029]FIG. 3 Means of Circuit Hierarchy Regeneration, PerformanceOptimization, Physical Layout Optimization, floor Planning, andExtracting Intellectual Property Circuit Cell Flow Chart

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Turning now descriptively to the drawings, in which similarreference characters denote similar elements throughout the severalviews, the attached figures illustrate a signal flow driven circuitanalysis and partition technique, which comprises automatic partition ofmixed signal integrated circuits based on functional blocks, automaticidentification of critical signal path in analog/RF circuits, automaticidentification of fundamental unit circuits, automatic identification ofmatching and symmetry requirement. Circuit partition automaticallypartitions a mixed signal circuit into blocks based on theirfunctionality. Identification of signal flow is achieved byautomatically tracing the signal flow and identifies the critical pathbased a set of rules. Various building blocks of known characteristicsand optimization requirement can also be automatically obtained. Bytracing the signal path, matching and symmetry requirement and parasiticloading requirement at critical circuit nodes can also be automaticallygenerated.

[0031] Circuit partition automatically partitions a mixed signal circuitinto blocks based on their functionality. Circuit partition is performedby tracing the input/output signals of the circuit according to a set of“tracing rules”: if a digital (analog) signal presents at the GATE of aMOSFET, then the SOURCE and DRAIN of this transistor is a digital(analog) node, unless it is terminated to supply rails (VCC or GND),denoted as: GATE—>SOURCE/DRAIN. We thus have: SOURCE—>DRAIN,DRAIN—>SOURCE, but not SOURCE or DRAIN—>GATE. On the other hand:resistors are transparent for both digital and analog signals,capacitors are transparent for analog signals but are open for digital,and inductors are mostly used as tuning load in RF circuits and rarelyfound in digital integrated circuits. Upon finishing of the tracing,circuit partition is obtained. Circuit partition rules can be changed toaccommodate other circuit topologies or requirement.

[0032] Identification of signal flow is achieved by automaticallytracing the signal flow and identifies the critical path based a set ofrules. The signal flow trackers does trace signal paths in RF/analogbock based on the rules: source to drain, drain to source, gate todrain, gate to source, but not drain to gate, not source to gate, andthe termination is PWR/GND pin and other signal pins. Critical signalpath is thus identified as those related to the critical input and/oroutput pins. With modified tracing rules, other circuit topologies canbe accommodated.

[0033] Various building blocks of known characteristics and optimizationrequirement can also be automatically obtained. Automatically identifiesthe fundamental unit circuit based on structure representation by signalflow analysis, unit circuits include, but not limited to, variousconfigurations of single stage amplifiers, current mirrors, differentialpairs and voltage and current references. Unit circuit identificationcan also be achieved with pattern matching. Unit circuit can be expandedto some more complex sub-circuits.

[0034] By tracing the signal path, matching and symmetry requirement andparasitic loading requirement at critical circuit nodes can also beautomatically generated. Automatically generates physical constraintssuch as matching, abutment and parasitic loading by a set of rule filesas defined in the operation descriptions. It is possible to perform somesimple numerical circuit simulation to enhance the constraintsgeneration.

[0035] All components in this invention can be performed in series or inparallel. Depending on the application, they each can be performedseparately if so desired: signal flow tracing and circuit partition in anumerical simulator, signal flow tracing and circuit partition in acircuit synthesizer, stand-alone signal flow driven circuit partitiontool.

[0036] A signal flow tracker starts from the input terminals, and tracesthe signals as the following: For MOSFET, gate—>drain/source,drain—>source, source—>drain; for resistor, one terminal—>anotherterminal; for capacitor and inductor, same as for resistor; theterminations of signal path is PWR/GND or output ports. The unit circuitexplorer works in two steps: first, unit circuit characterized structuregenerator produces the characteristic structure information, and thestructure explorer search the matched structures for specified unitcircuit. The matching explorer has three modules, differential pairexplorer, current source explorer, and signal-path matching explorer.The differential pair explorer tries to find the differential pair basedon the differential signal path. The two sides of differential pair mustbe matched. The current source explorer searches for the current sourcesand current mirrors, where the matched transistors are identified. Thesignal path matching explorer searches for matched signal flow pathsbased on the signal flow tracing.

[0037] The non-critical device explorer has three modules, the logicsignal tracker, the logic-driven-gate MOS explorer, and thecapacitor-connected MOS explorer. The logic signal flow tracker tracesthe logic according to the given rules. The logic-driven-gate MOSexplorer searches the MOSFETs whose gates are driven by the logicsignals. The capacitor-connected MOS explorer searches for the MOSFETsconnected as capacitors.

[0038] The bias circuit explorer has four modules, the unit circuitexplorer, matching explorer, not critical device explorer, and the biascircuit re-builder. The unit circuit explorer tries to dig out all theunit circuits, to make the bias circuit hierarchy. Matching explorertries to dig out the matching in the bias circuit. The not criticaldevice explorer tries to dig out all the not critical devices in thebias circuit. The bias circuit re-builder tries to re-build the biascircuit with the identified unit circuit as a sub-circuit.

[0039] In the core circuit explorer, the signal flow tracker tries toseparate the signal path for each critical signal; the zipper cellexplorer tries to dig out the common part of the two or more signalpaths, the signal path matching explorer tries to dig out the matchingbetween two signal paths, the unit circuit explorer tries to dig out theunit circuits in the core circuit, the core circuit re-builder tries tore-build the core circuit, with the zipper cell as a sub-circuit, theun-shared part of the signal path as a sub-circuit, the unit circuit ofthe signal path regarded as the sub-circuit in the signal pathsub-circuit, so that the core circuit is re-organized as a hierarchycircuit.

[0040] In the logic and analog/RF explorer, the signal flow trackerspread the logic signals or analog/RF signals from the input based onthe given rules; the devices with all terminals driven by logic signalare partitioned into logic circuits. Others are classified into theanalog/RF circuit. The logic circuit builder tries to build the logicsub-circuit; the analog circuit builder tries to build the analog/RFsub-circuit; and the whole circuit reorganized as the instantiation ofthe logic sub-circuit and the analog/RF sub-circuit. The logicsub-circuit will further handled by logic circuit explorer that is outof this invention.

[0041] The analog/RF circuit will be further handled by bias and corecircuit partitioner. The bias and core circuit partitioner tries topartition the analog/RF circuit into bias circuit and core circuit basedon the critical signal tracing. The analog/RF circuit re-organized asthe instantiations of bias sub-circuit and core sub-circuit. The biassub-circuit will be further handled by the bias circuit explorer and thecore sub-circuit will be further handled by the core circuit explorer.Therefore, a circuit will be re-organized as a new hierarchy circuitwith logic and analog/RF partitioned, bias and core partitioned, signalpath partitioned, unit circuit identified, symmetry and matchingidentified, etc., which will be potentially used for speeding up circuitsimulation, circuit optimization, yield improvement, efficientlycontrolling layout synthesis, circuit physical layout floor panning, andextracting Intellectual Property circuit cell for reuse, etc.

[0042] As to a further discussion of the manner of usage and operationof the present invention, the same should be apparent from the abovedescription. Accordingly, no further discussion relating to the mannerof usage and operation will be provided.

[0043] With respect to the above description then, it is to be realizedthat the optimum dimensional relationships for the parts of theinvention, to include variations in size, materials, shape, form,function and manner of operation, assembly and use, are deemed readilyapparent and obvious to one skilled in the art, and all equivalentrelationships to those illustrated in the drawings and described in thespecification are intended to be encompassed by the present invention.

[0044] Therefore, the foregoing is considered as illustrative only ofthe principles of the invention. Further, since numerous modificationsand changes will readily occur to those skilled in the art, it is notdesired to limit the invention to the exact construction and operationshown and described, and accordingly, all suitable modifications andequivalents may be resorted to, falling within the scope of theinvention.

1. A signal flow driven circuit analysis technique by tracing circuitsignal flow so that, analyzing a circuit, and partitioning a circuitbased on functionality and criticality, and generating multitude circuitlayout constraints are done by software program automatically.
 2. Thesignal flow driven circuit analysis technique of claim 1 comprising: (a)Providing a memory that is able to store a series of rules in saidmemory; and (b) Storing said series of rules in said memory; and (c)Providing a memory that is able to store a circuit netlist employinginput/output pin, any other terminal pins, power/ground terminals,active device elements, and passive device elements; and (d) Storingsaid circuit netlist in said memories; and (e) Utilizing said series ofrules to trace signal flow information and perform automatic circuitanalysis of said circuit netlist; and (f) Storing said signal flowinformation in said memory.
 3. The signal flow driven circuit analysistechnique of claim 2 further including a partition technique comprising:(a) Utilizing the signal flow driven circuit analysis technique of claim2 wherein said signal flow information to partition the circuit netlistof claim 2 into two parts: digital part and analog/RF part; and (b)Providing a memory that is able to store a series of critical signalflow requirements; and (c) Storing said series of critical signal flowrequirements in said memory; and (d) Utilizing said series of criticalsignal flow requirements to partition said analog/RF part in two parts:a biasing circuit part and a core signal flow path; and (e) Utilizingsaid series of critical signal flow requirements to identify an unitcircuit of current mirror, an unit circuit of differential pairs, anunit circuit of voltage reference, unite circuit of current reference,and an unite circuit of amplifier [etc.]; and (f) Utilizing said seriesof critical signal flow requirements to identify multitude criticalnodes, multitude critical nets, and multitude critical components in thecircuit netlist of claim 2; and (g) Providing a memory that is able tostore said critical nodes, said critical nets, and said criticalcomponents; and (h) Storing said critical nodes, said critical nets, andsaid critical components in said memory.
 4. The signal flow drivencircuit analysis technique of claim 1 further including a physicallayout constraint generation technique comprising: (a) Proving a memorythat is able to store a series of physical requirement rules; and (b)Storing said series of physical requirement rules in said memory; and(c) Utilizing the signal flow driven circuit analysis technique of claim2 wherein said signal flow information, and the signal flow drivencircuit partition technique of claim 3 wherein said critical nodes, saidcritical nets, said critical components, and said physical requirementrules to generate multitude circuit physical layout constraints ofmatching, abutment, symmetry, and parasitic loading; and Whereby anengineer can layout an analog circuit, a mixed signal circuit, and a RFcircuit automatically.
 5. A mean of circuit performance assessmentutilizing: (a) The signal flow driven circuit analysis technique ofclaim 2 wherein said signal flow information; and (b) The signal flowdriven circuit partition technique of claim 3 wherein said criticalnodes, and said critical nets, said critical components; and (c) Thephysical layout constraint generation technique of claim 4 wherein saidphysical requirement rules.
 6. A mean of circuit yield enhancementutilizing: (a) The signal flow driven circuit analysis technique ofclaim 2 wherein said signal flow information; and (b) The signal flowdriven circuit partition technique of claim 3 wherein said criticalnodes, and said critical nets, and said critical components; and (c) Thephysical layout constraint generation technique of claim 4 wherein saidphysical requirement rules to increase yield of analog circuit, and ofmixed signal circuit, and of RF circuit.
 7. A circuit hierarchyregeneration technique comprising: (a) The signal flow driven circuitanalysis technique of claim 2 wherein said signal flow information; and(b) The signal flow driven circuit partition technique of claim 3wherein said digital part, and said analog/RF part, and biasing circuitpart, and said core signal flow path, and said unit circuit; and (c) Thephysical layout constraint generation technique of claim 4 wherein saidcircuit physical layout constraints of matching, abutment, symmetry, andparasitic loading; and Whereby an engineer can improve an analogcircuit, mixed signal circuit, and RF circuit simulation speed.
 8. Acircuit performance optimization technique utilizing (a) The signal flowdriven circuit analysis technique of claim 2 wherein said signal flowinformation; and (b) The signal flow driven circuit partition techniqueof claim 3 wherein said digital part, and said analog/RF part, andbiasing circuit part, and said core signal flow path, and said unitcircuit; and (c) The physical layout constraint generation technique ofclaim 4 wherein said circuit physical layout constraints of matching,abutment, symmetry, and parasitic loading to optimize performance of ananalog circuit, and of a mixed signal circuit, and of a RF circuit.
 9. Acircuit physical layout optimization technique utilizing (a) The signalflow driven circuit analysis technique of claim 2 wherein said signalflow information; and (b) The signal flow driven circuit partitiontechnique of claim 3 wherein said digital part, and said analog/RF part,and biasing circuit part, and said core signal flow path, and said unitcircuit; and (c) The physical layout constraint generation technique ofclaim 4 wherein said circuit physical layout constraints of matching,abutment, symmetry, and parasitic loading to optimize a layout of analogcircuit, and of mixed signal circuit, and RF circuit.
 10. A mean ofcircuit physical layout floor planning utilizing: (a) The signal flowdriven circuit analysis technique of claim 2 wherein said signal flowinformation; and (b) The signal flow driven circuit partition techniqueof claim 3 wherein said digital part, and said analog/RF part, andbiasing circuit part, and said core signal flow path, and said unitcircuit; and (c) The physical layout constraint generation technique ofclaim 4 wherein said circuit physical layout constraints of matching,abutment, symmetry, and parasitic loading to optimize a layout of analogcircuit, and of mixed signal circuit, and RF circuit.
 11. A mean ofextracting Intellectual Property circuit cell utilizing: (a) The signalflow driven circuit analysis technique of claim 2 wherein said signalflow information; and (b) The signal flow driven circuit partitiontechnique of claim 3 wherein said digital part, and said analog/RF part,and biasing circuit part, and said core signal flow path, said unitcircuit; and (c) The physical layout constraint generation technique ofclaim 4 wherein said circuit physical layout constraints of matching,abutment, symmetry, and parasitic loading to reuse an IntellectualProperty circuit cell.